This is an example for driving the HDMI source port of the RealDigital Blackboard (a Zynq 7007S FPGA dev board) with a DVI video signal using the Spade HDL.

Building #

This project is designed to be built with the openXC7 toolchain. Swim (Spade's build tool) does not yet have integration with openXC7, so the standard openXC7 GNU make-based build system is used. Running make will automatically call spade build and then compile the bitstream using openXC7. Running make program with a Blackboard plugged in will automatically compile and program the design onto the board.

Functionality #

Displays various patterns (some of them animated), which can be selected between using switches 0-2 on the Blackboard.

Video modes #

The default video mode is 640x480@60Hz (which DVI/HDMI compliant monitors are required to support).

There are also commented out clock parameters in clock_gen.sv for:

1280x720@60Hz, CVT-RBv1 timings
1440x900@60Hz, CVT-RBv2 timings
840x525@60Hz, CVT-RBv1 timings

Changing the video mode is a somewhat manual process:

In src/main.spade, swap out low_pixel_format for one of the other relevant functions in spade_dvi::modes
In src/clock_gen.sv, comment out the parameters for 640x480@60Hz and uncomment the relevant set of parameters

Other modes are possible, but you will have to manually calculate the MMCME2 parameters for clock generation. This website is useful for calculating the MMCME2 parameters without the Vivado clock wizard. If you want to use a mode that isn't in spade_dvi::modes already, this website is useful for calculating video timings.

Note that if you try to use a mode with too high of a pixel clock you may experience artifacting or image dropouts. Note that not all of the modes in spade_dvi::modes will work on the Blackboard!