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Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198/* SPDX-License-Identifier: GPL-2.0-or-later *//* * OMAP GPIO handling defines and functions * * Copyright (C) 2003-2005 Nokia Corporation * * Written by Juha Yrjölä <juha.yrjola@nokia.com> */
#ifndef __ASM_ARCH_OMAP_GPIO_H#define __ASM_ARCH_OMAP_GPIO_H
#ifndef __ASSEMBLER__#include <linux/io.h>#include <linux/platform_device.h>#endif
#define OMAP1_MPUIO_BASE 0xfffb5000
/* * These are the omap15xx/16xx offsets. The omap7xx offset are * OMAP_MPUIO_ / 2 offsets below. */#define OMAP_MPUIO_INPUT_LATCH 0x00#define OMAP_MPUIO_OUTPUT 0x04#define OMAP_MPUIO_IO_CNTL 0x08#define OMAP_MPUIO_KBR_LATCH 0x10#define OMAP_MPUIO_KBC 0x14#define OMAP_MPUIO_GPIO_EVENT_MODE 0x18#define OMAP_MPUIO_GPIO_INT_EDGE 0x1c#define OMAP_MPUIO_KBD_INT 0x20#define OMAP_MPUIO_GPIO_INT 0x24#define OMAP_MPUIO_KBD_MASKIT 0x28#define OMAP_MPUIO_GPIO_MASKIT 0x2c#define OMAP_MPUIO_GPIO_DEBOUNCING 0x30#define OMAP_MPUIO_LATCH 0x34
#define OMAP34XX_NR_GPIOS 6
/* * OMAP1510 GPIO registers */#define OMAP1510_GPIO_DATA_INPUT 0x00#define OMAP1510_GPIO_DATA_OUTPUT 0x04#define OMAP1510_GPIO_DIR_CONTROL 0x08#define OMAP1510_GPIO_INT_CONTROL 0x0c#define OMAP1510_GPIO_INT_MASK 0x10#define OMAP1510_GPIO_INT_STATUS 0x14#define OMAP1510_GPIO_PIN_CONTROL 0x18
#define OMAP1510_IH_GPIO_BASE 64
/* * OMAP1610 specific GPIO registers */#define OMAP1610_GPIO_REVISION 0x0000#define OMAP1610_GPIO_SYSCONFIG 0x0010#define OMAP1610_GPIO_SYSSTATUS 0x0014#define OMAP1610_GPIO_IRQSTATUS1 0x0018#define OMAP1610_GPIO_IRQENABLE1 0x001c#define OMAP1610_GPIO_WAKEUPENABLE 0x0028#define OMAP1610_GPIO_DATAIN 0x002c#define OMAP1610_GPIO_DATAOUT 0x0030#define OMAP1610_GPIO_DIRECTION 0x0034#define OMAP1610_GPIO_EDGE_CTRL1 0x0038#define OMAP1610_GPIO_EDGE_CTRL2 0x003c#define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c#define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8#define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0#define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc#define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8#define OMAP1610_GPIO_SET_DATAOUT 0x00f0
/* * OMAP7XX specific GPIO registers */#define OMAP7XX_GPIO_DATA_INPUT 0x00#define OMAP7XX_GPIO_DATA_OUTPUT 0x04#define OMAP7XX_GPIO_DIR_CONTROL 0x08#define OMAP7XX_GPIO_INT_CONTROL 0x0c#define OMAP7XX_GPIO_INT_MASK 0x10#define OMAP7XX_GPIO_INT_STATUS 0x14
/* * omap2+ specific GPIO registers */#define OMAP24XX_GPIO_REVISION 0x0000#define OMAP24XX_GPIO_SYSCONFIG 0x0010#define OMAP24XX_GPIO_IRQSTATUS1 0x0018#define OMAP24XX_GPIO_IRQSTATUS2 0x0028#define OMAP24XX_GPIO_IRQENABLE2 0x002c#define OMAP24XX_GPIO_IRQENABLE1 0x001c#define OMAP24XX_GPIO_WAKE_EN 0x0020#define OMAP24XX_GPIO_CTRL 0x0030#define OMAP24XX_GPIO_OE 0x0034#define OMAP24XX_GPIO_DATAIN 0x0038#define OMAP24XX_GPIO_DATAOUT 0x003c#define OMAP24XX_GPIO_LEVELDETECT0 0x0040#define OMAP24XX_GPIO_LEVELDETECT1 0x0044#define OMAP24XX_GPIO_RISINGDETECT 0x0048#define OMAP24XX_GPIO_FALLINGDETECT 0x004c#define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050#define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054#define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060#define OMAP24XX_GPIO_SETIRQENABLE1 0x0064#define OMAP24XX_GPIO_CLEARWKUENA 0x0080#define OMAP24XX_GPIO_SETWKUENA 0x0084#define OMAP24XX_GPIO_CLEARDATAOUT 0x0090#define OMAP24XX_GPIO_SETDATAOUT 0x0094
#define OMAP4_GPIO_REVISION 0x0000#define OMAP4_GPIO_SYSCONFIG 0x0010#define OMAP4_GPIO_EOI 0x0020#define OMAP4_GPIO_IRQSTATUSRAW0 0x0024#define OMAP4_GPIO_IRQSTATUSRAW1 0x0028#define OMAP4_GPIO_IRQSTATUS0 0x002c#define OMAP4_GPIO_IRQSTATUS1 0x0030#define OMAP4_GPIO_IRQSTATUSSET0 0x0034#define OMAP4_GPIO_IRQSTATUSSET1 0x0038#define OMAP4_GPIO_IRQSTATUSCLR0 0x003c#define OMAP4_GPIO_IRQSTATUSCLR1 0x0040#define OMAP4_GPIO_IRQWAKEN0 0x0044#define OMAP4_GPIO_IRQWAKEN1 0x0048#define OMAP4_GPIO_IRQENABLE1 0x011c#define OMAP4_GPIO_WAKE_EN 0x0120#define OMAP4_GPIO_IRQSTATUS2 0x0128#define OMAP4_GPIO_IRQENABLE2 0x012c#define OMAP4_GPIO_CTRL 0x0130#define OMAP4_GPIO_OE 0x0134#define OMAP4_GPIO_DATAIN 0x0138#define OMAP4_GPIO_DATAOUT 0x013c#define OMAP4_GPIO_LEVELDETECT0 0x0140#define OMAP4_GPIO_LEVELDETECT1 0x0144#define OMAP4_GPIO_RISINGDETECT 0x0148#define OMAP4_GPIO_FALLINGDETECT 0x014c#define OMAP4_GPIO_DEBOUNCENABLE 0x0150#define OMAP4_GPIO_DEBOUNCINGTIME 0x0154#define OMAP4_GPIO_CLEARIRQENABLE1 0x0160#define OMAP4_GPIO_SETIRQENABLE1 0x0164#define OMAP4_GPIO_CLEARWKUENA 0x0180#define OMAP4_GPIO_SETWKUENA 0x0184#define OMAP4_GPIO_CLEARDATAOUT 0x0190#define OMAP4_GPIO_SETDATAOUT 0x0194
#define OMAP_MAX_GPIO_LINES 192
#ifndef __ASSEMBLER__struct omap_gpio_reg_offs { u16 revision; u16 sysconfig; u16 direction; u16 datain; u16 dataout; u16 set_dataout; u16 clr_dataout; u16 irqstatus; u16 irqstatus2; u16 irqstatus_raw0; u16 irqstatus_raw1; u16 irqenable; u16 irqenable2; u16 set_irqenable; u16 clr_irqenable; u16 debounce; u16 debounce_en; u16 ctrl; u16 wkup_en; u16 leveldetect0; u16 leveldetect1; u16 risingdetect; u16 fallingdetect; u16 irqctrl; u16 edgectrl1; u16 edgectrl2; u16 pinctrl;
bool irqenable_inv;};
struct omap_gpio_platform_data { int bank_type; int bank_width; /* GPIO bank width */ int bank_stride; /* Only needed for omap1 MPUIO */ bool dbck_flag; /* dbck required or not - True for OMAP3&4 */ bool loses_context; /* whether the bank would ever lose context */ bool is_mpuio; /* whether the bank is of type MPUIO */ u32 non_wakeup_gpios;
const struct omap_gpio_reg_offs *regs;
/* Return context loss count due to PM states changing */ int (*get_context_loss_count)(struct device *dev);};
#endif /* __ASSEMBLER__ */
#endif