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(I'm so sorry!) Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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#ifndef _LINUX_CORESIGHT_H#define _LINUX_CORESIGHT_H
#include <linux/amba/bus.h>#include <linux/clk.h>#include <linux/device.h>#include <linux/io.h>#include <linux/perf_event.h>#include <linux/sched.h>#include <linux/platform_device.h>
/* Peripheral id registers (0xFD0-0xFEC) */#define CORESIGHT_PERIPHIDR4 0xfd0#define CORESIGHT_PERIPHIDR5 0xfd4#define CORESIGHT_PERIPHIDR6 0xfd8#define CORESIGHT_PERIPHIDR7 0xfdC#define CORESIGHT_PERIPHIDR0 0xfe0#define CORESIGHT_PERIPHIDR1 0xfe4#define CORESIGHT_PERIPHIDR2 0xfe8#define CORESIGHT_PERIPHIDR3 0xfeC/* Component id registers (0xFF0-0xFFC) */#define CORESIGHT_COMPIDR0 0xff0#define CORESIGHT_COMPIDR1 0xff4#define CORESIGHT_COMPIDR2 0xff8#define CORESIGHT_COMPIDR3 0xffC
#define ETM_ARCH_V3_3 0x23#define ETM_ARCH_V3_5 0x25#define PFT_ARCH_V1_0 0x30#define PFT_ARCH_V1_1 0x31
#define CORESIGHT_UNLOCK 0xc5acce55
extern const struct bus_type coresight_bustype;
enum coresight_dev_type { CORESIGHT_DEV_TYPE_SINK, CORESIGHT_DEV_TYPE_LINK, CORESIGHT_DEV_TYPE_LINKSINK, CORESIGHT_DEV_TYPE_SOURCE, CORESIGHT_DEV_TYPE_HELPER, CORESIGHT_DEV_TYPE_MAX};
enum coresight_dev_subtype_sink { CORESIGHT_DEV_SUBTYPE_SINK_DUMMY, CORESIGHT_DEV_SUBTYPE_SINK_PORT, CORESIGHT_DEV_SUBTYPE_SINK_BUFFER, CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM, CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM,};
enum coresight_dev_subtype_link { CORESIGHT_DEV_SUBTYPE_LINK_MERG, CORESIGHT_DEV_SUBTYPE_LINK_SPLIT, CORESIGHT_DEV_SUBTYPE_LINK_FIFO,};
enum coresight_dev_subtype_source { CORESIGHT_DEV_SUBTYPE_SOURCE_PROC, CORESIGHT_DEV_SUBTYPE_SOURCE_BUS, CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE, CORESIGHT_DEV_SUBTYPE_SOURCE_TPDM, CORESIGHT_DEV_SUBTYPE_SOURCE_OTHERS,};
enum coresight_dev_subtype_helper { CORESIGHT_DEV_SUBTYPE_HELPER_CATU, CORESIGHT_DEV_SUBTYPE_HELPER_ECT_CTI, CORESIGHT_DEV_SUBTYPE_HELPER_CTCU,};
/** * union coresight_dev_subtype - further characterisation of a type * @sink_subtype: type of sink this component is, as defined * by @coresight_dev_subtype_sink. * @link_subtype: type of link this component is, as defined * by @coresight_dev_subtype_link. * @source_subtype: type of source this component is, as defined * by @coresight_dev_subtype_source. * @helper_subtype: type of helper this component is, as defined * by @coresight_dev_subtype_helper. */union coresight_dev_subtype { /* We have some devices which acts as LINK and SINK */ struct { enum coresight_dev_subtype_sink sink_subtype; enum coresight_dev_subtype_link link_subtype; }; enum coresight_dev_subtype_source source_subtype; enum coresight_dev_subtype_helper helper_subtype;};
/** * struct coresight_platform_data - data harvested from the firmware * specification. * * @nr_inconns: Number of elements for the input connections. * @nr_outconns: Number of elements for the output connections. * @out_conns: Array of nr_outconns pointers to connections from this * component. * @in_conns: Sparse array of pointers to input connections. Sparse * because the source device owns the connection so when it's * unloaded the connection leaves an empty slot. */struct coresight_platform_data { int nr_inconns; int nr_outconns; struct coresight_connection **out_conns; struct coresight_connection **in_conns;};
/** * struct csdev_access - Abstraction of a CoreSight device access. * * @io_mem : True if the device has memory mapped I/O * @base : When io_mem == true, base address of the component * @read : Read from the given "offset" of the given instance. * @write : Write "val" to the given "offset". */struct csdev_access { bool io_mem; union { void __iomem *base; struct { u64 (*read)(u32 offset, bool relaxed, bool _64bit); void (*write)(u64 val, u32 offset, bool relaxed, bool _64bit); }; };};
#define CSDEV_ACCESS_IOMEM(_addr) \ ((struct csdev_access) { \ .io_mem = true, \ .base = (_addr), \ })
#define CORESIGHT_DESC_CPU_BOUND BIT(0)/* Device can't be activated from sysfs, only via Perf. */#define CORESIGHT_DESC_NO_SYSFS_MODE BIT(1)
/** * struct coresight_desc - description of a component required from drivers * @type: as defined by @coresight_dev_type. * @subtype: as defined by @coresight_dev_subtype. * @ops: generic operations for this component, as defined * by @coresight_ops. * @pdata: platform data collected from DT. * @dev: The device entity associated to this component. * @groups: operations specific to this component. These will end up * in the component's sysfs sub-directory. * @name: name for the coresight device, also shown under sysfs. * @access: Describe access to the device * @flags: The descritpion flags. * @cpu: The CPU this component is affined to. */struct coresight_desc { enum coresight_dev_type type; union coresight_dev_subtype subtype; const struct coresight_ops *ops; struct coresight_platform_data *pdata; struct device *dev; const struct attribute_group **groups; const char *name; struct csdev_access access; u32 flags; int cpu;};
/** * struct coresight_connection - representation of a single connection * @src_port: a connection's output port number. * @dest_port: destination's input port number @src_port is connected to. * @dest_fwnode: destination component's fwnode handle. * @dest_dev: a @coresight_device representation of the component connected to @src_port. NULL until the device is created * @link: Representation of the connection as a sysfs link. * @filter_src_fwnode: filter source component's fwnode handle. * @filter_src_dev: a @coresight_device representation of the component that needs to be filtered. * * The full connection structure looks like this, where in_conns store * references to same connection as the source device's out_conns. * * +-----------------------------+ +-----------------------------+ * |coresight_device | |coresight_connection | * |-----------------------------| |-----------------------------| * | | | | * | | | dest_dev*|<-- * |pdata->out_conns[nr_outconns]|<->|src_dev* | | * | | | | | * +-----------------------------+ +-----------------------------+ | * | * +-----------------------------+ | * |coresight_device | | * |------------------------------ | * | | | * | pdata->in_conns[nr_inconns]|<-- * | | * +-----------------------------+ */struct coresight_connection { int src_port; int dest_port; struct fwnode_handle *dest_fwnode; struct coresight_device *dest_dev; struct coresight_sysfs_link *link; struct coresight_device *src_dev; struct fwnode_handle *filter_src_fwnode; struct coresight_device *filter_src_dev; int src_refcnt; int dest_refcnt;};
/** * struct coresight_sysfs_link - representation of a connection in sysfs. * @orig: Originating (master) coresight device for the link. * @orig_name: Name to use for the link orig->target. * @target: Target (slave) coresight device for the link. * @target_name: Name to use for the link target->orig. */struct coresight_sysfs_link { struct coresight_device *orig; const char *orig_name; struct coresight_device *target; const char *target_name;};
/* architecturally we have 128 IDs some of which are reserved */#define CORESIGHT_TRACE_IDS_MAX 128
/** * Trace ID map. * * @used_ids: Bitmap to register available (bit = 0) and in use (bit = 1) IDs. * Initialised so that the reserved IDs are permanently marked as * in use. * @perf_cs_etm_session_active: Number of Perf sessions using this ID map. */struct coresight_trace_id_map { DECLARE_BITMAP(used_ids, CORESIGHT_TRACE_IDS_MAX); atomic_t __percpu *cpu_map; atomic_t perf_cs_etm_session_active; raw_spinlock_t lock;};
/** * struct coresight_device - representation of a device as used by the framework * @pdata: Platform data with device connections associated to this device. * @type: as defined by @coresight_dev_type. * @subtype: as defined by @coresight_dev_subtype. * @ops: generic operations for this component, as defined * by @coresight_ops. * @access: Device i/o access abstraction for this device. * @dev: The device entity associated to this component. * @path: Activated path pointer (only used for source device). * @mode: The device mode, i.e sysFS, Perf or disabled. This is actually * an 'enum cs_mode' but stored in an atomic type. Access is always * through atomic APIs, ensuring SMP-safe synchronisation between * racing from sysFS and Perf mode. A compare-and-exchange * operation is done to atomically claim one mode or the other. * @refcnt: keep track of what is in use. Only access this outside of the * device's spinlock when the coresight_mutex held and mode == * CS_MODE_SYSFS. Otherwise it must be accessed from inside the * spinlock. * @cpu: The CPU this component is affined to (-1 for not CPU bound). * @orphan: true if the component has connections that haven't been linked. * @sysfs_sink_activated: 'true' when a sink has been selected for use via sysfs * by writing a 1 to the 'enable_sink' file. A sink can be * activated but not yet enabled. Enabling for a _sink_ happens * when a source has been selected and a path is enabled from * source to that sink. A sink can also become enabled but not * activated if it's used via Perf. * @ea: Device attribute for sink representation under PMU directory. * @def_sink: cached reference to default sink found for this device. * @nr_links: number of sysfs links created to other components from this * device. These will appear in the "connections" group. * @has_conns_grp: Have added a "connections" group for sysfs links. * @feature_csdev_list: List of complex feature programming added to the device. * @config_csdev_list: List of system configurations added to the device. * @cscfg_csdev_lock: Protect the lists of configurations and features. * @active_cscfg_ctxt: Context information for current active system configuration. */struct coresight_device { struct coresight_platform_data *pdata; enum coresight_dev_type type; union coresight_dev_subtype subtype; const struct coresight_ops *ops; struct csdev_access access; struct device dev; struct coresight_path *path; atomic_t mode; int refcnt; int cpu; bool orphan; /* sink specific fields */ bool sysfs_sink_activated; struct dev_ext_attribute *ea; struct coresight_device *def_sink; struct coresight_trace_id_map perf_sink_id_map; /* sysfs links between components */ int nr_links; bool has_conns_grp; /* system configuration and feature lists */ struct list_head feature_csdev_list; struct list_head config_csdev_list; raw_spinlock_t cscfg_csdev_lock; void *active_cscfg_ctxt; /* CORESIGHT_DESC_[x] flags */ u32 flags;};
/* * coresight_dev_list - Mapping for devices to "name" index for device * names. * * @node: Node on the global device index list. * @nr_idx: Number of entries already allocated. * @pfx: Prefix pattern for device name. * @fwnode_list: Array of fwnode_handles associated with each allocated * index, upto nr_idx entries. */struct coresight_dev_list { struct list_head node; int nr_idx; char *pfx; struct fwnode_handle **fwnode_list;};
#define to_coresight_device(d) container_of(d, struct coresight_device, dev)
/** * struct coresight_path - data needed by enable/disable path * @path_list: path from source to sink. * @trace_id: trace_id of the whole path. * @handle: handle of the aux_event. */struct coresight_path { struct list_head path_list; u8 trace_id; struct perf_output_handle *handle;};
enum cs_mode { CS_MODE_DISABLED = 0, CS_MODE_SYSFS = BIT(0), CS_MODE_PERF = BIT(1),};
#define coresight_ops(csdev) csdev->ops#define source_ops(csdev) csdev->ops->source_ops#define sink_ops(csdev) csdev->ops->sink_ops#define link_ops(csdev) csdev->ops->link_ops#define helper_ops(csdev) csdev->ops->helper_ops#define ect_ops(csdev) csdev->ops->ect_ops#define panic_ops(csdev) csdev->ops->panic_ops
/** * struct coresight_ops_sink - basic operations for a sink * Operations available for sinks * @enable: enables the sink. * @disable: disables the sink. * @alloc_buffer: initialises perf's ring buffer for trace collection. * @free_buffer: release memory allocated in @get_config. * @update_buffer: update buffer pointers after a trace session. */struct coresight_ops_sink { int (*enable)(struct coresight_device *csdev, enum cs_mode mode, struct coresight_path *path); int (*disable)(struct coresight_device *csdev); void *(*alloc_buffer)(struct coresight_device *csdev, struct perf_event *event, void **pages, int nr_pages, bool overwrite); void (*free_buffer)(void *config); unsigned long (*update_buffer)(struct coresight_device *csdev, struct perf_output_handle *handle, void *sink_config);};
/** * struct coresight_ops_link - basic operations for a link * Operations available for links. * @enable: enables flow between iport and oport. * @disable: disables flow between iport and oport. */struct coresight_ops_link { int (*enable)(struct coresight_device *csdev, struct coresight_connection *in, struct coresight_connection *out); void (*disable)(struct coresight_device *csdev, struct coresight_connection *in, struct coresight_connection *out);};
/** * struct coresight_ops_source - basic operations for a source * Operations available for sources. * @enable: enables tracing for a source. * @disable: disables tracing for a source. * @resume_perf: resumes tracing for a source in perf session. * @pause_perf: pauses tracing for a source in perf session. */struct coresight_ops_source { int (*enable)(struct coresight_device *csdev, struct perf_event *event, enum cs_mode mode, struct coresight_path *path); void (*disable)(struct coresight_device *csdev, struct perf_event *event); int (*resume_perf)(struct coresight_device *csdev); void (*pause_perf)(struct coresight_device *csdev);};
/** * struct coresight_ops_helper - Operations for a helper device. * * All operations could pass in a device specific data, which could * help the helper device to determine what to do. * * @enable : Enable the device * @disable : Disable the device */struct coresight_ops_helper { int (*enable)(struct coresight_device *csdev, enum cs_mode mode, struct coresight_path *path); int (*disable)(struct coresight_device *csdev, struct coresight_path *path);};
/** * struct coresight_ops_panic - Generic device ops for panic handing * * @sync : Sync the device register state/trace data */struct coresight_ops_panic { int (*sync)(struct coresight_device *csdev);};
struct coresight_ops { int (*trace_id)(struct coresight_device *csdev, enum cs_mode mode, struct coresight_device *sink); int (*pm_save_disable)(struct coresight_device *csdev); void (*pm_restore_enable)(struct coresight_device *csdev); const struct coresight_ops_sink *sink_ops; const struct coresight_ops_link *link_ops; const struct coresight_ops_source *source_ops; const struct coresight_ops_helper *helper_ops; const struct coresight_ops_panic *panic_ops;};
static inline u32 csdev_access_relaxed_read32(struct csdev_access *csa, u32 offset){ if (likely(csa->io_mem)) return readl_relaxed(csa->base + offset);
return csa->read(offset, true, false);}
#define CORESIGHT_CIDRn(i) (0xFF0 + ((i) * 4))
static inline u32 coresight_get_cid(void __iomem *base){ u32 i, cid = 0;
for (i = 0; i < 4; i++) cid |= readl(base + CORESIGHT_CIDRn(i)) << (i * 8);
return cid;}
static inline bool is_coresight_device(void __iomem *base){ u32 cid = coresight_get_cid(base);
return cid == CORESIGHT_CID;}
#define CORESIGHT_PIDRn(i) (0xFE0 + ((i) * 4))
static inline u32 coresight_get_pid(struct csdev_access *csa){ u32 i, pid = 0;
for (i = 0; i < 4; i++) pid |= csdev_access_relaxed_read32(csa, CORESIGHT_PIDRn(i)) << (i * 8);
return pid;}
static inline u64 csdev_access_relaxed_read_pair(struct csdev_access *csa, u32 lo_offset, u32 hi_offset){ if (likely(csa->io_mem)) { return readl_relaxed(csa->base + lo_offset) | ((u64)readl_relaxed(csa->base + hi_offset) << 32); }
return csa->read(lo_offset, true, false) | (csa->read(hi_offset, true, false) << 32);}
static inline void csdev_access_relaxed_write_pair(struct csdev_access *csa, u64 val, u32 lo_offset, u32 hi_offset){ if (likely(csa->io_mem)) { writel_relaxed((u32)val, csa->base + lo_offset); writel_relaxed((u32)(val >> 32), csa->base + hi_offset); } else { csa->write((u32)val, lo_offset, true, false); csa->write((u32)(val >> 32), hi_offset, true, false); }}
static inline u32 csdev_access_read32(struct csdev_access *csa, u32 offset){ if (likely(csa->io_mem)) return readl(csa->base + offset);
return csa->read(offset, false, false);}
static inline void csdev_access_relaxed_write32(struct csdev_access *csa, u32 val, u32 offset){ if (likely(csa->io_mem)) writel_relaxed(val, csa->base + offset); else csa->write(val, offset, true, false);}
static inline void csdev_access_write32(struct csdev_access *csa, u32 val, u32 offset){ if (likely(csa->io_mem)) writel(val, csa->base + offset); else csa->write(val, offset, false, false);}
#ifdef CONFIG_64BIT
static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa, u32 offset){ if (likely(csa->io_mem)) return readq_relaxed(csa->base + offset);
return csa->read(offset, true, true);}
static inline u64 csdev_access_read64(struct csdev_access *csa, u32 offset){ if (likely(csa->io_mem)) return readq(csa->base + offset);
return csa->read(offset, false, true);}
static inline void csdev_access_relaxed_write64(struct csdev_access *csa, u64 val, u32 offset){ if (likely(csa->io_mem)) writeq_relaxed(val, csa->base + offset); else csa->write(val, offset, true, true);}
static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 offset){ if (likely(csa->io_mem)) writeq(val, csa->base + offset); else csa->write(val, offset, false, true);}
#else /* !CONFIG_64BIT */
static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa, u32 offset){ WARN_ON(1); return 0;}
static inline u64 csdev_access_read64(struct csdev_access *csa, u32 offset){ WARN_ON(1); return 0;}
static inline void csdev_access_relaxed_write64(struct csdev_access *csa, u64 val, u32 offset){ WARN_ON(1);}
static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 offset){ WARN_ON(1);}#endif /* CONFIG_64BIT */
static inline bool coresight_is_device_source(struct coresight_device *csdev){ return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SOURCE);}
static inline bool coresight_is_percpu_source(struct coresight_device *csdev){ return csdev && coresight_is_device_source(csdev) && (csdev->subtype.source_subtype == CORESIGHT_DEV_SUBTYPE_SOURCE_PROC);}
static inline bool coresight_is_software_source(struct coresight_device *csdev){ return csdev && coresight_is_device_source(csdev) && (csdev->subtype.source_subtype == CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE);}
static inline bool coresight_is_percpu_sink(struct coresight_device *csdev){ return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SINK) && (csdev->subtype.sink_subtype == CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM);}
/* * Atomically try to take the device and set a new mode. Returns true on * success, false if the device is already taken by someone else. */static inline bool coresight_take_mode(struct coresight_device *csdev, enum cs_mode new_mode){ int curr = CS_MODE_DISABLED;
return atomic_try_cmpxchg_acquire(&csdev->mode, &curr, new_mode);}
static inline enum cs_mode coresight_get_mode(struct coresight_device *csdev){ return atomic_read_acquire(&csdev->mode);}
static inline void coresight_set_mode(struct coresight_device *csdev, enum cs_mode new_mode){ enum cs_mode current_mode = coresight_get_mode(csdev);
/* * Changing to a new mode must be done from an already disabled state * unless it's synchronized with coresight_take_mode(). Otherwise the * device is already in use and signifies a locking issue. */ WARN(new_mode != CS_MODE_DISABLED && current_mode != CS_MODE_DISABLED && current_mode != new_mode, "Device already in use\n");
atomic_set_release(&csdev->mode, new_mode);}
struct coresight_device *coresight_register(struct coresight_desc *desc);void coresight_unregister(struct coresight_device *csdev);int coresight_enable_sysfs(struct coresight_device *csdev);void coresight_disable_sysfs(struct coresight_device *csdev);int coresight_timeout(struct csdev_access *csa, u32 offset, int position, int value);typedef void (*coresight_timeout_cb_t) (struct csdev_access *, u32, int, int);int coresight_timeout_action(struct csdev_access *csa, u32 offset, int position, int value, coresight_timeout_cb_t cb);int coresight_claim_device(struct coresight_device *csdev);int coresight_claim_device_unlocked(struct coresight_device *csdev);
int coresight_claim_device(struct coresight_device *csdev);int coresight_claim_device_unlocked(struct coresight_device *csdev);void coresight_clear_self_claim_tag(struct csdev_access *csa);void coresight_clear_self_claim_tag_unlocked(struct csdev_access *csa);void coresight_disclaim_device(struct coresight_device *csdev);void coresight_disclaim_device_unlocked(struct coresight_device *csdev);char *coresight_alloc_device_name(const char *prefix, struct device *dev);
bool coresight_loses_context_with_cpu(struct device *dev);
u32 coresight_relaxed_read32(struct coresight_device *csdev, u32 offset);u32 coresight_read32(struct coresight_device *csdev, u32 offset);void coresight_write32(struct coresight_device *csdev, u32 val, u32 offset);void coresight_relaxed_write32(struct coresight_device *csdev, u32 val, u32 offset);u64 coresight_relaxed_read64(struct coresight_device *csdev, u32 offset);u64 coresight_read64(struct coresight_device *csdev, u32 offset);void coresight_relaxed_write64(struct coresight_device *csdev, u64 val, u32 offset);void coresight_write64(struct coresight_device *csdev, u64 val, u32 offset);
int coresight_get_cpu(struct device *dev);int coresight_get_static_trace_id(struct device *dev, u32 *id);
struct coresight_platform_data *coresight_get_platform_data(struct device *dev);struct coresight_connection *coresight_add_out_conn(struct device *dev, struct coresight_platform_data *pdata, const struct coresight_connection *new_conn);int coresight_add_in_conn(struct coresight_connection *conn);struct coresight_device *coresight_find_input_type(struct coresight_platform_data *pdata, enum coresight_dev_type type, union coresight_dev_subtype subtype);struct coresight_device *coresight_find_output_type(struct coresight_platform_data *pdata, enum coresight_dev_type type, union coresight_dev_subtype subtype);
int coresight_init_driver_with_owner(const char *drv, struct amba_driver *amba_drv, struct platform_driver *pdev_drv, struct module *owner, const char *mod_name);#define coresight_init_driver(drv, amba_drv, pdev_drv) \ coresight_init_driver_with_owner(drv, amba_drv, pdev_drv, THIS_MODULE, KBUILD_MODNAME)
void coresight_remove_driver(struct amba_driver *amba_drv, struct platform_driver *pdev_drv);int coresight_etm_get_trace_id(struct coresight_device *csdev, enum cs_mode mode, struct coresight_device *sink);int coresight_get_enable_clocks(struct device *dev, struct clk **pclk, struct clk **atclk);#endif /* _LINUX_COREISGHT_H */