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(I'm so sorry!) Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270// SPDX-License-Identifier: MIT/* * Copyright 2022 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: AMD * */
#include "dm_services_types.h"
#include "amdgpu.h"#include "amdgpu_dm.h"#include "amdgpu_dm_wb.h"#include "dm_helpers.h"#include "amdgpu_display.h"#include "dc.h"
#include <drm/drm_edid.h>#include <drm/drm_atomic_state_helper.h>#include <drm/drm_modeset_helper_vtables.h>
static const u32 amdgpu_dm_wb_formats[] = { DRM_FORMAT_XRGB2101010,};
#if IS_ENABLED(CONFIG_DRM_AMD_DC_KUNIT_TEST)static const struct amdgpu_dm_wb_kunit_ops amdgpu_dm_wb_default_ops = { .reserve = amdgpu_bo_reserve, .reserve_fences = dma_resv_reserve_fences, .pin = amdgpu_bo_pin, .alloc_gart = amdgpu_ttm_alloc_gart, .unreserve = amdgpu_bo_unreserve, .gpu_offset = amdgpu_bo_gpu_offset, .ref = amdgpu_bo_ref, .unpin = amdgpu_bo_unpin, .unref = amdgpu_bo_unref,};
static const struct amdgpu_dm_wb_kunit_ops *amdgpu_dm_wb_ops = &amdgpu_dm_wb_default_ops;
void amdgpu_dm_wb_kunit_set_ops(const struct amdgpu_dm_wb_kunit_ops *ops){ amdgpu_dm_wb_ops = ops ? ops : &amdgpu_dm_wb_default_ops;}EXPORT_IF_KUNIT(amdgpu_dm_wb_kunit_set_ops);
#define wb_bo_reserve amdgpu_dm_wb_ops->reserve#define wb_dma_resv_reserve_fences amdgpu_dm_wb_ops->reserve_fences#define wb_bo_pin amdgpu_dm_wb_ops->pin#define wb_ttm_alloc_gart amdgpu_dm_wb_ops->alloc_gart#define wb_bo_unreserve amdgpu_dm_wb_ops->unreserve#define wb_bo_gpu_offset amdgpu_dm_wb_ops->gpu_offset#define wb_bo_ref amdgpu_dm_wb_ops->ref#define wb_bo_unpin amdgpu_dm_wb_ops->unpin#define wb_bo_unref amdgpu_dm_wb_ops->unref
#else
#define wb_bo_reserve amdgpu_bo_reserve#define wb_dma_resv_reserve_fences dma_resv_reserve_fences#define wb_bo_pin amdgpu_bo_pin#define wb_ttm_alloc_gart amdgpu_ttm_alloc_gart#define wb_bo_unreserve amdgpu_bo_unreserve#define wb_bo_gpu_offset amdgpu_bo_gpu_offset#define wb_bo_ref amdgpu_bo_ref#define wb_bo_unpin amdgpu_bo_unpin#define wb_bo_unref amdgpu_bo_unref
#endif
STATIC_IFN_KUNIT int amdgpu_dm_wb_encoder_atomic_check(struct drm_encoder *encoder, struct drm_crtc_state *crtc_state, struct drm_connector_state *conn_state){ struct drm_framebuffer *fb; const struct drm_display_mode *mode = &crtc_state->mode; bool found = false; uint8_t i;
if (!conn_state->writeback_job || !conn_state->writeback_job->fb) return 0;
fb = conn_state->writeback_job->fb; if (fb->width != mode->hdisplay || fb->height != mode->vdisplay) { DRM_DEBUG_KMS("Invalid framebuffer size %ux%u\n", fb->width, fb->height); return -EINVAL; }
for (i = 0; i < ARRAY_SIZE(amdgpu_dm_wb_formats); i++) { if (fb->format->format == amdgpu_dm_wb_formats[i]) { found = true; break; } }
if (!found) { DRM_DEBUG_KMS("Invalid pixel format %p4cc\n", &fb->format->format); return -EINVAL; }
return 0;}EXPORT_IF_KUNIT(amdgpu_dm_wb_encoder_atomic_check);
STATIC_IFN_KUNIT int amdgpu_dm_wb_connector_get_modes(struct drm_connector *connector){ /* Maximum resolution supported by DWB */ return drm_add_modes_noedid(connector, 3840, 2160);}EXPORT_IF_KUNIT(amdgpu_dm_wb_connector_get_modes);
STATIC_IFN_KUNIT int amdgpu_dm_wb_prepare_job(struct drm_writeback_connector *wb_connector, struct drm_writeback_job *job){ struct amdgpu_framebuffer *afb; struct drm_gem_object *obj; struct amdgpu_device *adev; struct amdgpu_bo *rbo; uint32_t domain; int r;
if (!job->fb) { DRM_DEBUG_KMS("No FB bound\n"); return 0; }
afb = to_amdgpu_framebuffer(job->fb); obj = job->fb->obj[0]; rbo = gem_to_amdgpu_bo(obj); adev = amdgpu_ttm_adev(rbo->tbo.bdev);
r = wb_bo_reserve(rbo, true); if (r) { drm_err(adev_to_drm(adev), "fail to reserve bo: %pe\n", ERR_PTR(r)); return r; }
r = wb_dma_resv_reserve_fences(rbo->tbo.base.resv, TTM_NUM_MOVE_FENCES); if (r) { drm_err(adev_to_drm(adev), "reserving fence slot failed: %pe\n", ERR_PTR(r)); goto error_unlock; }
domain = amdgpu_display_supported_domains(adev, rbo->flags);
rbo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; r = wb_bo_pin(rbo, domain); if (unlikely(r != 0)) { if (r != -ERESTARTSYS) DRM_ERROR("Failed to pin framebuffer: %pe\n", ERR_PTR(r)); goto error_unlock; }
r = wb_ttm_alloc_gart(&rbo->tbo); if (unlikely(r != 0)) { DRM_ERROR("%p bind failed: %pe\n", rbo, ERR_PTR(r)); goto error_unpin; }
wb_bo_unreserve(rbo);
afb->address = wb_bo_gpu_offset(rbo);
wb_bo_ref(rbo);
return 0;
error_unpin: wb_bo_unpin(rbo);
error_unlock: wb_bo_unreserve(rbo); return r;}EXPORT_IF_KUNIT(amdgpu_dm_wb_prepare_job);
STATIC_IFN_KUNIT void amdgpu_dm_wb_cleanup_job(struct drm_writeback_connector *connector, struct drm_writeback_job *job){ struct amdgpu_bo *rbo; int r;
if (!job->fb) return;
rbo = gem_to_amdgpu_bo(job->fb->obj[0]); r = wb_bo_reserve(rbo, false); if (unlikely(r)) { DRM_ERROR("failed to reserve rbo before unpin: %pe\n", ERR_PTR(r)); return; }
wb_bo_unpin(rbo); wb_bo_unreserve(rbo); wb_bo_unref(&rbo);}EXPORT_IF_KUNIT(amdgpu_dm_wb_cleanup_job);
static const struct drm_encoder_helper_funcs amdgpu_dm_wb_encoder_helper_funcs = { .atomic_check = amdgpu_dm_wb_encoder_atomic_check,};
static const struct drm_connector_funcs amdgpu_dm_wb_connector_funcs = { .fill_modes = drm_helper_probe_single_connector_modes, .destroy = drm_connector_cleanup, .reset = amdgpu_dm_connector_funcs_reset, .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state, .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,};
static const struct drm_connector_helper_funcs amdgpu_dm_wb_conn_helper_funcs = { .get_modes = amdgpu_dm_wb_connector_get_modes, .prepare_writeback_job = amdgpu_dm_wb_prepare_job, .cleanup_writeback_job = amdgpu_dm_wb_cleanup_job,};
int amdgpu_dm_wb_connector_init(struct amdgpu_display_manager *dm, struct amdgpu_dm_wb_connector *wbcon, uint32_t link_index){ struct dc *dc = dm->dc; struct dc_link *link = dc_get_link_at_index(dc, link_index); int res;
wbcon->link = link;
drm_connector_helper_add(&wbcon->base.base, &amdgpu_dm_wb_conn_helper_funcs);
res = drm_writeback_connector_init(&dm->adev->ddev, &wbcon->base, &amdgpu_dm_wb_connector_funcs, &amdgpu_dm_wb_encoder_helper_funcs, amdgpu_dm_wb_formats, ARRAY_SIZE(amdgpu_dm_wb_formats), amdgpu_dm_get_encoder_crtc_mask(dm->adev));
if (res) return res; /* * Some of the properties below require access to state, like bpc. * Allocate some default initial connector state with our reset helper. */ if (wbcon->base.base.funcs->reset) wbcon->base.base.funcs->reset(&wbcon->base.base);
return 0;}EXPORT_IF_KUNIT(amdgpu_dm_wb_connector_init);