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(I'm so sorry!) Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426// SPDX-License-Identifier: MIT/* * Copyright 2026 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: AMD * */
#include <drm/drm_atomic.h>#include <drm/drm_modes.h>#include <drm/drm_vblank.h>
#include "dc.h"#include "amdgpu.h"#include "amdgpu_dm.h"#include "amdgpu_dm_crtc.h"#include "amdgpu_dm_psr.h"#include "amdgpu_dm_replay.h"#include "amdgpu_dm_freesync.h"#include "dm_helpers.h"#include "modules/inc/mod_freesync.h"#include "modules/inc/mod_info_packet.h"
bool amdgpu_dm_is_dc_timing_adjust_needed(struct dm_crtc_state *old_state, struct dm_crtc_state *new_state){ if (new_state->stream->adjust.timing_adjust_pending) return true; if (new_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) return true; else if (amdgpu_dm_crtc_vrr_active(old_state) != amdgpu_dm_crtc_vrr_active(new_state)) return true; else return false;}EXPORT_IF_KUNIT(amdgpu_dm_is_dc_timing_adjust_needed);
boolamdgpu_dm_is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state, struct drm_crtc_state *new_crtc_state){ const struct drm_display_mode *old_mode, *new_mode;
if (!old_crtc_state || !new_crtc_state) return false;
old_mode = &old_crtc_state->mode; new_mode = &new_crtc_state->mode;
if (old_mode->clock == new_mode->clock && old_mode->hdisplay == new_mode->hdisplay && old_mode->vdisplay == new_mode->vdisplay && old_mode->htotal == new_mode->htotal && old_mode->vtotal != new_mode->vtotal && old_mode->hsync_start == new_mode->hsync_start && old_mode->vsync_start != new_mode->vsync_start && old_mode->hsync_end == new_mode->hsync_end && old_mode->vsync_end != new_mode->vsync_end && old_mode->hskew == new_mode->hskew && old_mode->vscan == new_mode->vscan && (old_mode->vsync_end - old_mode->vsync_start) == (new_mode->vsync_end - new_mode->vsync_start)) return true;
return false;}EXPORT_IF_KUNIT(amdgpu_dm_is_timing_unchanged_for_freesync);
void amdgpu_dm_set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state){ u64 num, den, res; struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base;
dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED;
num = (unsigned long long)new_crtc_state->mode.clock * 1000 * 1000000; den = (unsigned long long)new_crtc_state->mode.htotal * (unsigned long long)new_crtc_state->mode.vtotal;
res = div_u64(num, den); dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res;}EXPORT_IF_KUNIT(amdgpu_dm_set_freesync_fixed_config);
void amdgpu_dm_reset_freesync_config_for_crtc( struct dm_crtc_state *new_crtc_state){ new_crtc_state->vrr_supported = false;
memset(&new_crtc_state->vrr_infopacket, 0, sizeof(new_crtc_state->vrr_infopacket)); memset(&new_crtc_state->vtem_infopacket, 0, sizeof(new_crtc_state->vtem_infopacket));}EXPORT_IF_KUNIT(amdgpu_dm_reset_freesync_config_for_crtc);
void amdgpu_dm_get_freesync_config_for_crtc( struct dm_crtc_state *new_crtc_state, struct dm_connector_state *new_con_state){ struct mod_freesync_config config = {0}; struct amdgpu_dm_connector *aconnector; struct drm_display_mode *mode = &new_crtc_state->base.mode; int vrefresh = drm_mode_vrefresh(mode); bool fs_vid_mode = false;
if (new_con_state->base.connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) return;
aconnector = to_amdgpu_dm_connector(new_con_state->base.connector);
new_crtc_state->vrr_supported = new_con_state->freesync_capable && vrefresh >= aconnector->min_vfreq && vrefresh <= aconnector->max_vfreq;
if (new_crtc_state->vrr_supported) { new_crtc_state->stream->ignore_msa_timing_param = true; fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000; config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000; config.vsif_supported = true; config.btr = true;
if (fs_vid_mode) { config.state = VRR_STATE_ACTIVE_FIXED; config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz; goto out; } else if (new_crtc_state->base.vrr_enabled) { config.state = VRR_STATE_ACTIVE_VARIABLE; } else { config.state = VRR_STATE_INACTIVE; } } else { config.state = VRR_STATE_UNSUPPORTED; }out: new_crtc_state->freesync_config = config;
drm_dbg_driver(new_con_state->base.connector->dev, "VRR: cfg vrr_enabled=%d vrr_supported=%d fs_capable=%d vrefresh=%d min=%d max=%d state=%d\n", new_crtc_state->base.vrr_enabled, new_crtc_state->vrr_supported, new_con_state->freesync_capable, vrefresh, aconnector->min_vfreq, aconnector->max_vfreq, config.state);}EXPORT_IF_KUNIT(amdgpu_dm_get_freesync_config_for_crtc);
void amdgpu_dm_update_freesync_state_on_stream( struct amdgpu_display_manager *dm, struct dm_crtc_state *new_crtc_state, struct dc_stream_state *new_stream, struct dc_plane_state *surface, u32 flip_timestamp_in_us){ struct mod_vrr_params vrr_params; struct dc_info_packet vrr_infopacket = {0}; struct dc_info_packet vtem_infopacket = {0}; struct amdgpu_device *adev = dm->adev; struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc); unsigned long flags; bool pack_sdp_v1_3 = false; struct amdgpu_dm_connector *aconn; enum vrr_packet_type packet_type = PACKET_TYPE_VRR;
if (!new_stream) return;
/* * TODO: Determine why min/max totals and vrefresh can be 0 here. * For now it's sufficient to just guard against these conditions. */
if (!new_stream->timing.h_total || !new_stream->timing.v_total) return;
spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); vrr_params = acrtc->dm_irq_params.vrr_params;
if (surface) { mod_freesync_handle_preflip( dm->freesync_module, surface, new_stream, flip_timestamp_in_us, &vrr_params);
if (adev->family < AMDGPU_FAMILY_AI && amdgpu_dm_crtc_vrr_active(new_crtc_state)) { mod_freesync_handle_v_update(dm->freesync_module, new_stream, &vrr_params);
/* Need to call this before the frame ends. */ dc_stream_adjust_vmin_vmax(dm->dc, new_crtc_state->stream, &vrr_params.adjust); } }
aconn = (struct amdgpu_dm_connector *)new_stream->dm_stream_context;
if (aconn && (aconn->as_type == FREESYNC_TYPE_PCON_IN_WHITELIST || aconn->vsdb_info.replay_mode)) { pack_sdp_v1_3 = aconn->pack_sdp_v1_3;
if (aconn->vsdb_info.amd_vsdb_version == 1) packet_type = PACKET_TYPE_FS_V1; else if (aconn->vsdb_info.amd_vsdb_version == 2) packet_type = PACKET_TYPE_FS_V2; else if (aconn->vsdb_info.amd_vsdb_version == 3) packet_type = PACKET_TYPE_FS_V3;
mod_build_adaptive_sync_infopacket(new_stream, aconn->as_type, NULL, &new_stream->adaptive_sync_infopacket); }
mod_freesync_build_vrr_infopacket( dm->freesync_module, new_stream, &vrr_params, packet_type, TRANSFER_FUNC_UNKNOWN, &vrr_infopacket, pack_sdp_v1_3);
/* * If the sink does not support FreeSync, but it does support VRR, * we need to build a VTEM packet to enable VRR. */ if (aconn && !aconn->vsdb_info.freesync_supported && aconn->base.display_info.hdmi.vrr_cap.supported && (new_stream->signal == SIGNAL_TYPE_HDMI_FRL || new_stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)) { mod_build_infopacket_vtem(new_stream, &vrr_params, 0, &vtem_infopacket); memset(&vrr_infopacket, 0, sizeof(vrr_infopacket)); }
new_crtc_state->freesync_vrr_info_changed |= (memcmp(&new_crtc_state->vrr_infopacket, &vrr_infopacket, sizeof(vrr_infopacket)) != 0);
new_crtc_state->freesync_vrr_info_changed |= (memcmp(&new_crtc_state->vtem_infopacket, &vtem_infopacket, sizeof(vtem_infopacket)) != 0);
acrtc->dm_irq_params.vrr_params = vrr_params; new_crtc_state->vrr_infopacket = vrr_infopacket; new_crtc_state->vtem_infopacket = vtem_infopacket;
new_stream->vrr_infopacket = vrr_infopacket; new_stream->vtem_infopacket = vtem_infopacket; new_stream->allow_freesync = mod_freesync_get_freesync_enabled(&vrr_params);
/* * HDMI ALLM: when Gaming-VRR is active (VRR_EN=1) and the sink * advertises ALLM in the SCDS, the Source shall transmit the HF-VSIF * with ALLM_Mode=1 (HDMI 2.1 Section 7.6.6). */ if (new_stream->signal == SIGNAL_TYPE_HDMI_TYPE_A || new_stream->signal == SIGNAL_TYPE_HDMI_FRL) { struct dc_info_packet vsp_infopacket = {0}; bool sink_allm = aconn && aconn->base.display_info.hdmi.allm; bool allm = sink_allm && (vrr_params.state == VRR_STATE_ACTIVE_VARIABLE || vrr_params.state == VRR_STATE_ACTIVE_FIXED); bool allm_changed;
mod_build_hf_vsif_infopacket(new_stream, &vsp_infopacket, allm, allm);
allm_changed = memcmp(&new_stream->vsp_infopacket, &vsp_infopacket, sizeof(vsp_infopacket)) != 0; new_crtc_state->freesync_vrr_info_changed |= allm_changed; new_stream->vsp_infopacket = vsp_infopacket;
if (allm_changed) drm_dbg_driver(adev_to_drm(adev), "ALLM: flip on crtc=%u: sink_allm=%d vrr_state=%d -> ALLM_Mode=%d\n", new_crtc_state->base.crtc->base.id, sink_allm, vrr_params.state, allm); }
if (new_crtc_state->freesync_vrr_info_changed) drm_dbg_kms(adev_to_drm(adev), "VRR packet update: crtc=%u enabled=%d state=%d", new_crtc_state->base.crtc->base.id, (int)new_crtc_state->base.vrr_enabled, (int)vrr_params.state);
spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);}EXPORT_IF_KUNIT(amdgpu_dm_update_freesync_state_on_stream);
void amdgpu_dm_update_stream_irq_parameters( struct amdgpu_display_manager *dm, struct dm_crtc_state *new_crtc_state){ struct dc_stream_state *new_stream = new_crtc_state->stream; struct mod_vrr_params vrr_params; struct mod_freesync_config config = new_crtc_state->freesync_config; struct amdgpu_device *adev = dm->adev; struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc); unsigned long flags;
if (!new_stream) return;
/* * TODO: Determine why min/max totals and vrefresh can be 0 here. * For now it's sufficient to just guard against these conditions. */ if (!new_stream->timing.h_total || !new_stream->timing.v_total) return;
spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); vrr_params = acrtc->dm_irq_params.vrr_params;
if (new_crtc_state->vrr_supported && config.min_refresh_in_uhz && config.max_refresh_in_uhz) { /* * if freesync compatible mode was set, config.state will be set * in atomic check */ if (config.state == VRR_STATE_ACTIVE_FIXED && config.fixed_refresh_in_uhz && (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) || new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)) { vrr_params.max_refresh_in_uhz = config.max_refresh_in_uhz; vrr_params.min_refresh_in_uhz = config.min_refresh_in_uhz; vrr_params.fixed_refresh_in_uhz = config.fixed_refresh_in_uhz; vrr_params.state = VRR_STATE_ACTIVE_FIXED; } else { config.state = new_crtc_state->base.vrr_enabled ? VRR_STATE_ACTIVE_VARIABLE : VRR_STATE_INACTIVE; } } else { config.state = VRR_STATE_UNSUPPORTED; }
mod_freesync_build_vrr_params(dm->freesync_module, new_stream, &config, &vrr_params);
new_crtc_state->freesync_config = config; /* Copy state for access from DM IRQ handler */ acrtc->dm_irq_params.freesync_config = config; acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes; acrtc->dm_irq_params.vrr_params = vrr_params; spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);}EXPORT_IF_KUNIT(amdgpu_dm_update_stream_irq_parameters);
void amdgpu_dm_handle_vrr_transition(struct amdgpu_display_manager *dm, struct dm_crtc_state *old_state, struct dm_crtc_state *new_state){ struct amdgpu_device *adev = dm->adev; bool old_vrr_active = amdgpu_dm_crtc_vrr_active(old_state); bool new_vrr_active = amdgpu_dm_crtc_vrr_active(new_state);
/* Only DCE gates vupdate on VRR, keep it enabled for DCN */ bool vrr_gates_vupdate = amdgpu_ip_version(adev, DCE_HWIP, 0) == 0;
if (!old_vrr_active && new_vrr_active) { /* Transition VRR inactive -> active: * While VRR is active, we must not disable vblank irq, as a * reenable after disable would compute bogus vblank/pflip * timestamps if it likely happened inside display front-porch. * * We also need vupdate irq for the actual core vblank handling * at end of vblank. */ if (vrr_gates_vupdate) WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, true) != 0); WARN_ON(drm_crtc_vblank_get(new_state->base.crtc) != 0); drm_dbg_driver(new_state->base.crtc->dev, "%s: crtc=%u VRR off->on: Get vblank ref\n", __func__, new_state->base.crtc->base.id);
scoped_guard(mutex, &dm->dc_lock) { dc_exit_ips_for_hw_access(dm->dc); amdgpu_dm_psr_set_event(dm, new_state->stream, true, psr_event_vrr_transition, true); amdgpu_dm_replay_set_event(dm, new_state->stream, true, replay_event_vrr, true); } } else if (old_vrr_active && !new_vrr_active) { /* Transition VRR active -> inactive: * Allow vblank irq disable again for fixed refresh rate. */ if (vrr_gates_vupdate) WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, false) != 0); drm_crtc_vblank_put(new_state->base.crtc); drm_dbg_driver(new_state->base.crtc->dev, "%s: crtc=%u VRR on->off: Drop vblank ref\n", __func__, new_state->base.crtc->base.id);
scoped_guard(mutex, &dm->dc_lock) { dc_exit_ips_for_hw_access(dm->dc); amdgpu_dm_psr_set_event(dm, new_state->stream, false, psr_event_vrr_transition, false); amdgpu_dm_replay_set_event(dm, new_state->stream, false, replay_event_vrr, false); } }}EXPORT_IF_KUNIT(amdgpu_dm_handle_vrr_transition);