Something went wrong. Try again.
(I'm so sorry!) Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
Something went wrong. Try again.
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854// SPDX-License-Identifier: MIT/* * Copyright 2022 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: AMD * */#include <drm/drm_vblank.h>#include <drm/drm_atomic_helper.h>
#include "dc.h"#include "amdgpu.h"#include "amdgpu_dm_psr.h"#include "amdgpu_dm_replay.h"#include "amdgpu_dm_crtc.h"#include "amdgpu_dm_irq.h"#include "amdgpu_dm_plane.h"#include "amdgpu_dm_trace.h"#include "amdgpu_dm_debugfs.h"#include "dm_helpers.h"#include "modules/inc/mod_power.h"
#define HPD_DETECTION_PERIOD_uS 2000000#define HPD_DETECTION_TIME_uS 100000
void amdgpu_dm_crtc_handle_vblank(struct amdgpu_crtc *acrtc){ struct drm_crtc *crtc = &acrtc->base; struct drm_device *dev = crtc->dev; unsigned long flags;
drm_crtc_handle_vblank(crtc);
spin_lock_irqsave(&dev->event_lock, flags);
/* Send completion event for cursor-only commits */ if (acrtc->event && acrtc->pflip_status != AMDGPU_FLIP_SUBMITTED) { drm_crtc_send_vblank_event(crtc, acrtc->event); drm_crtc_vblank_put(crtc); acrtc->event = NULL; }
spin_unlock_irqrestore(&dev->event_lock, flags);}EXPORT_IF_KUNIT(amdgpu_dm_crtc_handle_vblank);
bool amdgpu_dm_crtc_modeset_required(struct drm_crtc_state *crtc_state, struct dc_stream_state *new_stream, struct dc_stream_state *old_stream){ return crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);}EXPORT_IF_KUNIT(amdgpu_dm_crtc_modeset_required);
bool amdgpu_dm_crtc_vrr_active_irq(struct amdgpu_crtc *acrtc)
{ return acrtc->dm_irq_params.freesync_config.state == VRR_STATE_ACTIVE_VARIABLE || acrtc->dm_irq_params.freesync_config.state == VRR_STATE_ACTIVE_FIXED;}EXPORT_IF_KUNIT(amdgpu_dm_crtc_vrr_active_irq);
int amdgpu_dm_crtc_set_vupdate_irq(struct drm_crtc *crtc, bool enable){ enum dc_irq_source irq_source; struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); struct amdgpu_device *adev = drm_to_adev(crtc->dev); int rc;
if (acrtc->otg_inst == -1) return 0;
irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst;
rc = amdgpu_dm_irq_set(adev, irq_source, enable) ? 0 : -EBUSY;
DRM_DEBUG_VBL("crtc %d - vupdate irq %sabling: r=%d\n", acrtc->crtc_id, enable ? "en" : "dis", rc); return rc;}EXPORT_IF_KUNIT(amdgpu_dm_crtc_set_vupdate_irq);
bool amdgpu_dm_crtc_vrr_active(const struct dm_crtc_state *dm_state){ return dm_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE || dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;}EXPORT_IF_KUNIT(amdgpu_dm_crtc_vrr_active);
/** * amdgpu_dm_crtc_set_static_screen_optimze() - Toggle static screen optimizations. * * @dm: display manager * @stream: DC stream state * @sso_enable: desired static screen optimization state * @allow_sr_entry: whether entry into self-refresh mode is allowed * * This function uses the static-screen optimization state as the trigger to * set/clear the Replay and PSR vsync-related events. */void amdgpu_dm_crtc_set_static_screen_optimze( struct amdgpu_display_manager *dm, struct dc_stream_state *stream, bool sso_enable, bool allow_sr_entry){ struct dc_link *link = stream->link; bool set_vsync_event = !sso_enable;
/* * allow_sr_entry gates only entry. A disable request must still set * the vsync events to force Replay and PSR1 out and keep them blocked. */ if (sso_enable && !allow_sr_entry) return;
amdgpu_dm_replay_set_event(dm, stream, set_vsync_event, replay_event_vsync, set_vsync_event);
if (link->psr_settings.psr_version < DC_PSR_VERSION_SU_1) amdgpu_dm_psr_set_event(dm, stream, set_vsync_event, psr_event_vsync, set_vsync_event);}EXPORT_IF_KUNIT(amdgpu_dm_crtc_set_static_screen_optimze);
bool amdgpu_dm_is_headless(struct amdgpu_device *adev){ struct drm_connector *connector; struct drm_connector_list_iter iter; struct drm_device *dev; bool is_headless = true;
if (adev == NULL) return true;
dev = adev->dm.ddev;
drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) {
if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) continue;
if (connector->status == connector_status_connected) { is_headless = false; break; } } drm_connector_list_iter_end(&iter); return is_headless;}EXPORT_IF_KUNIT(amdgpu_dm_is_headless);
STATIC_IFN_KUNIT void amdgpu_dm_idle_worker(struct work_struct *work){ struct idle_workqueue *idle_work;
idle_work = container_of(work, struct idle_workqueue, work); idle_work->dm->idle_workqueue->running = true;
while (idle_work->enable) { fsleep(HPD_DETECTION_PERIOD_uS); mutex_lock(&idle_work->dm->dc_lock); if (!idle_work->dm->dc->idle_optimizations_allowed) { mutex_unlock(&idle_work->dm->dc_lock); break; } dc_allow_idle_optimizations(idle_work->dm->dc, false);
mutex_unlock(&idle_work->dm->dc_lock); fsleep(HPD_DETECTION_TIME_uS); mutex_lock(&idle_work->dm->dc_lock);
if (!amdgpu_dm_is_headless(idle_work->dm->adev) && !amdgpu_dm_psr_is_active_allowed(idle_work->dm)) { mutex_unlock(&idle_work->dm->dc_lock); break; }
if (idle_work->enable) { dc_post_update_surfaces_to_stream(idle_work->dm->dc); dc_allow_idle_optimizations(idle_work->dm->dc, true); } mutex_unlock(&idle_work->dm->dc_lock); } idle_work->dm->idle_workqueue->running = false;}EXPORT_IF_KUNIT(amdgpu_dm_idle_worker);
struct idle_workqueue *idle_create_workqueue(struct amdgpu_device *adev){ struct idle_workqueue *idle_work;
idle_work = kzalloc_obj(*idle_work); if (ZERO_OR_NULL_PTR(idle_work)) return NULL;
idle_work->dm = &adev->dm; idle_work->enable = false; idle_work->running = false; INIT_WORK(&idle_work->work, amdgpu_dm_idle_worker);
return idle_work;}EXPORT_IF_KUNIT(idle_create_workqueue);
STATIC_IFN_KUNIT void amdgpu_dm_crtc_vblank_control_worker(struct work_struct *work){ struct vblank_control_work *vblank_work = container_of(work, struct vblank_control_work, work); struct amdgpu_display_manager *dm = vblank_work->dm;
mutex_lock(&dm->dc_lock);
if (vblank_work->enable) { dm->active_vblank_irq_count++; amdgpu_dm_ism_commit_event(&vblank_work->acrtc->ism, DM_ISM_EVENT_EXIT_IDLE_REQUESTED); } else { if (dm->active_vblank_irq_count > 0) dm->active_vblank_irq_count--; amdgpu_dm_ism_commit_event(&vblank_work->acrtc->ism, DM_ISM_EVENT_ENTER_IDLE_REQUESTED); }
mutex_unlock(&dm->dc_lock);
dc_stream_release(vblank_work->stream);
kfree(vblank_work);}EXPORT_IF_KUNIT(amdgpu_dm_crtc_vblank_control_worker);
#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) || IS_ENABLED(CONFIG_DRM_AMD_DC_KUNIT_TEST)STATIC_IFN_KUNIT int amdgpu_dm_crtc_set_vline0_irq(struct drm_crtc *crtc, int irq_type, bool enable){ struct amdgpu_device *adev = drm_to_adev(crtc->dev); int rc;
/* crtc vline0 interrupt, only available on DCN+ */ if (amdgpu_ip_version(adev, DCE_HWIP, 0) == 0) return 0;
if (enable) { rc = amdgpu_irq_get(adev, &adev->vline0_irq, irq_type); drm_dbg_vbl(crtc->dev, "Get vline0_irq ret=%d\n", rc); } else { rc = amdgpu_irq_put(adev, &adev->vline0_irq, irq_type); drm_dbg_vbl(crtc->dev, "Put vline0_irq ret=%d\n", rc); }
return rc;}EXPORT_IF_KUNIT(amdgpu_dm_crtc_set_vline0_irq);#endif
static inline int amdgpu_dm_crtc_set_vblank(struct drm_crtc *crtc, bool enable){ struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); struct amdgpu_device *adev = drm_to_adev(crtc->dev); struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state); struct amdgpu_display_manager *dm = &adev->dm; struct vblank_control_work *work; int irq_type; int rc = 0;
if (enable && !acrtc->base.enabled) { drm_dbg_vbl(crtc->dev, "Reject vblank enable on unconfigured CRTC %d (enabled=%d)\n", acrtc->crtc_id, acrtc->base.enabled); return -EINVAL; }
irq_type = amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id);
if (enable && acrtc_state->stream) { struct dc *dc = adev->dm.dc; struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc); struct psr_settings *psr = &acrtc_state->stream->link->psr_settings; struct replay_settings *pr = &acrtc_state->stream->link->replay_settings; bool sr_supported = (psr->psr_version != DC_PSR_VERSION_UNSUPPORTED) || pr->config.replay_supported;
/* * IPS & self-refresh feature can cause vblank counter resets between * vblank disable and enable. * It may cause system stuck due to waiting for the vblank counter. * Call this function to estimate missed vblanks by using timestamps and * update the vblank counter in DRM. */ if (dc->caps.ips_support && dc->config.disable_ips != DMUB_IPS_DISABLE_ALL && sr_supported && vblank->config.disable_immediate) drm_crtc_vblank_restore(crtc); }
/* * On DCN, VUPDATE_NO_LOCK is the single OTG interrupt used to deliver * vblank and pageflip completion events, so enable it whenever vblank * is enabled. On DCE, vupdate is only needed in VRR mode. */ if (amdgpu_ip_version(adev, DCE_HWIP, 0) != 0) { if (enable) { rc = amdgpu_irq_get(adev, &adev->vupdate_irq, irq_type); drm_dbg_vbl(crtc->dev, "Get vupdate_irq ret=%d\n", rc); } else { rc = amdgpu_irq_put(adev, &adev->vupdate_irq, irq_type); drm_dbg_vbl(crtc->dev, "Put vupdate_irq ret=%d\n", rc); } } else if (dc_supports_vrr(dm->dc->ctx->dce_version)) { if (enable) { /* vblank irq on -> Only need vupdate irq in vrr mode * Not ref-counted since we need explicit enable/disable * for DCE VRR handling */ if (amdgpu_dm_crtc_vrr_active(acrtc_state)) rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, true); } else { /* vblank irq off -> vupdate irq off */ rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, false); } }
if (rc) return rc;
/* * VLINE0 (crtc_irq) and GRPH_PFLIP (pageflip_irq) are only used on * DCE. On DCN, vblank and pageflip completion are delivered from * VUPDATE_NO_LOCK (enabled above), so don't touch them here. */ if (amdgpu_ip_version(adev, DCE_HWIP, 0) == 0) { /* crtc vblank or vstartup interrupt */ if (enable) { rc = amdgpu_irq_get(adev, &adev->crtc_irq, irq_type); drm_dbg_vbl(crtc->dev, "Get crtc_irq ret=%d\n", rc); } else { rc = amdgpu_irq_put(adev, &adev->crtc_irq, irq_type); drm_dbg_vbl(crtc->dev, "Put crtc_irq ret=%d\n", rc); }
if (rc) return rc;
/* * hubp surface flip interrupt * * We have no guarantee that the frontend index maps to the same * backend index - some even map to more than one. * * TODO: Use a different interrupt or check DC itself for the mapping. */ if (enable) { rc = amdgpu_irq_get(adev, &adev->pageflip_irq, irq_type); drm_dbg_vbl(crtc->dev, "Get pageflip_irq ret=%d\n", rc); } else { rc = amdgpu_irq_put(adev, &adev->pageflip_irq, irq_type); drm_dbg_vbl(crtc->dev, "Put pageflip_irq ret=%d\n", rc); }
if (rc) return rc; }
#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) rc = amdgpu_dm_crtc_set_vline0_irq(crtc, irq_type, enable); if (rc) return rc;#endif
if (amdgpu_in_reset(adev)) return 0;
if (dm->vblank_control_workqueue) { work = kzalloc_obj(*work, GFP_ATOMIC); if (!work) return -ENOMEM;
INIT_WORK(&work->work, amdgpu_dm_crtc_vblank_control_worker); work->dm = dm; work->acrtc = acrtc; work->enable = enable;
if (acrtc_state->stream) { dc_stream_retain(acrtc_state->stream); work->stream = acrtc_state->stream; }
queue_work(dm->vblank_control_workqueue, &work->work); }
return 0;}
int amdgpu_dm_crtc_enable_vblank(struct drm_crtc *crtc){ return amdgpu_dm_crtc_set_vblank(crtc, true);}EXPORT_IF_KUNIT(amdgpu_dm_crtc_enable_vblank);
void amdgpu_dm_crtc_disable_vblank(struct drm_crtc *crtc){ amdgpu_dm_crtc_set_vblank(crtc, false);}EXPORT_IF_KUNIT(amdgpu_dm_crtc_disable_vblank);
STATIC_IFN_KUNIT void amdgpu_dm_crtc_destroy_state(struct drm_crtc *crtc, struct drm_crtc_state *state){ struct dm_crtc_state *cur = to_dm_crtc_state(state);
/* TODO Destroy dc_stream objects are stream object is flattened */ if (cur->stream) dc_stream_release(cur->stream);
__drm_atomic_helper_crtc_destroy_state(state);
kfree(state);}EXPORT_IF_KUNIT(amdgpu_dm_crtc_destroy_state);
STATIC_IFN_KUNIT struct drm_crtc_state *amdgpu_dm_crtc_duplicate_state(struct drm_crtc *crtc){ struct dm_crtc_state *state, *cur;
cur = to_dm_crtc_state(crtc->state);
if (WARN_ON(!crtc->state)) return NULL;
state = kzalloc_obj(*state); if (!state) return NULL;
__drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
if (cur->stream) { state->stream = cur->stream; dc_stream_retain(state->stream); }
state->active_planes = cur->active_planes; state->vrr_infopacket = cur->vrr_infopacket; state->abm_level = cur->abm_level; state->vrr_supported = cur->vrr_supported; state->freesync_config = cur->freesync_config; state->cm_has_degamma = cur->cm_has_degamma; state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb; state->regamma_tf = cur->regamma_tf; state->crc_skip_count = cur->crc_skip_count; state->mpo_requested = cur->mpo_requested; state->cursor_mode = cur->cursor_mode; /* TODO Duplicate dc_stream after objects are stream object is flattened */
return &state->base;}EXPORT_IF_KUNIT(amdgpu_dm_crtc_duplicate_state);
STATIC_IFN_KUNIT void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc){ /* * ISM workers are intentionally quiesced by amdgpu_dm_ism_disable() * in amdgpu_dm_fini(). That must happen before dc_destroy() so ISM * cannot access an invalid dc handle once dc is released. */
drm_crtc_cleanup(crtc); kfree(crtc);}EXPORT_IF_KUNIT(amdgpu_dm_crtc_destroy);
STATIC_IFN_KUNIT struct drm_crtc_state *amdgpu_dm_crtc_create_state(struct drm_crtc *crtc){ struct dm_crtc_state *state;
state = kzalloc_obj(*state); if (!state) return ERR_PTR(-ENOMEM);
__drm_atomic_helper_crtc_state_init(&state->base, crtc);
return &state->base;}EXPORT_IF_KUNIT(amdgpu_dm_crtc_create_state);
#ifdef CONFIG_DEBUG_FSSTATIC_IFN_KUNIT int amdgpu_dm_crtc_late_register(struct drm_crtc *crtc){ crtc_debugfs_init(crtc);
return 0;}EXPORT_IF_KUNIT(amdgpu_dm_crtc_late_register);#endif
#ifdef AMD_PRIVATE_COLOR/** * dm_crtc_additional_color_mgmt - enable additional color properties * @crtc: DRM CRTC * * This function lets the driver enable post-blending CRTC regamma transfer * function property in addition to DRM CRTC gamma LUT. Default value means * linear transfer function, which is the default CRTC gamma LUT behaviour * without this property. */static voiddm_crtc_additional_color_mgmt(struct drm_crtc *crtc){ struct amdgpu_device *adev = drm_to_adev(crtc->dev);
if (adev->dm.dc->caps.color.mpc.ogam_ram) drm_object_attach_property(&crtc->base, adev->mode_info.regamma_tf_property, AMDGPU_TRANSFER_FUNCTION_DEFAULT);}
static intamdgpu_dm_atomic_crtc_set_property(struct drm_crtc *crtc, struct drm_crtc_state *state, struct drm_property *property, uint64_t val){ struct amdgpu_device *adev = drm_to_adev(crtc->dev); struct dm_crtc_state *acrtc_state = to_dm_crtc_state(state);
if (property == adev->mode_info.regamma_tf_property) { if (acrtc_state->regamma_tf != val) { acrtc_state->regamma_tf = val; acrtc_state->base.color_mgmt_changed |= 1; } } else { drm_dbg_atomic(crtc->dev, "[CRTC:%d:%s] unknown property [PROP:%d:%s]]\n", crtc->base.id, crtc->name, property->base.id, property->name); return -EINVAL; }
return 0;}
static intamdgpu_dm_atomic_crtc_get_property(struct drm_crtc *crtc, const struct drm_crtc_state *state, struct drm_property *property, uint64_t *val){ struct amdgpu_device *adev = drm_to_adev(crtc->dev); struct dm_crtc_state *acrtc_state = to_dm_crtc_state(state);
if (property == adev->mode_info.regamma_tf_property) *val = acrtc_state->regamma_tf; else return -EINVAL;
return 0;}#endif
/* Implemented only the options currently available for the driver */static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = { .atomic_create_state = amdgpu_dm_crtc_create_state, .destroy = amdgpu_dm_crtc_destroy, .set_config = drm_atomic_helper_set_config, .page_flip = drm_atomic_helper_page_flip, .atomic_duplicate_state = amdgpu_dm_crtc_duplicate_state, .atomic_destroy_state = amdgpu_dm_crtc_destroy_state, .set_crc_source = amdgpu_dm_crtc_set_crc_source, .verify_crc_source = amdgpu_dm_crtc_verify_crc_source, .get_crc_sources = amdgpu_dm_crtc_get_crc_sources, .get_vblank_counter = amdgpu_get_vblank_counter_kms, .enable_vblank = amdgpu_dm_crtc_enable_vblank, .disable_vblank = amdgpu_dm_crtc_disable_vblank, .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,#if defined(CONFIG_DEBUG_FS) .late_register = amdgpu_dm_crtc_late_register,#endif#ifdef AMD_PRIVATE_COLOR .atomic_set_property = amdgpu_dm_atomic_crtc_set_property, .atomic_get_property = amdgpu_dm_atomic_crtc_get_property,#endif};
static void amdgpu_dm_crtc_helper_disable(struct drm_crtc *crtc){}
STATIC_IFN_KUNIT int amdgpu_dm_crtc_count_crtc_active_planes(struct drm_crtc_state *new_crtc_state){ struct drm_atomic_commit *state = new_crtc_state->state; struct drm_plane *plane; int num_active = 0;
drm_for_each_plane_mask(plane, state->dev, new_crtc_state->plane_mask) { struct drm_plane_state *new_plane_state;
/* Cursor planes are "fake". */ if (plane->type == DRM_PLANE_TYPE_CURSOR) continue;
new_plane_state = drm_atomic_get_new_plane_state(state, plane);
if (!new_plane_state) { /* * The plane is enable on the CRTC and hasn't changed * state. This means that it previously passed * validation and is therefore enabled. */ num_active += 1; continue; }
/* We need a framebuffer to be considered enabled. */ num_active += (new_plane_state->fb != NULL); }
return num_active;}EXPORT_IF_KUNIT(amdgpu_dm_crtc_count_crtc_active_planes);
STATIC_IFN_KUNIT void amdgpu_dm_crtc_update_crtc_active_planes(struct drm_crtc *crtc, struct drm_crtc_state *new_crtc_state){ struct dm_crtc_state *dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
dm_new_crtc_state->active_planes = 0;
if (!dm_new_crtc_state->stream) return;
dm_new_crtc_state->active_planes = amdgpu_dm_crtc_count_crtc_active_planes(new_crtc_state);}EXPORT_IF_KUNIT(amdgpu_dm_crtc_update_crtc_active_planes);
STATIC_IFN_KUNIT bool amdgpu_dm_crtc_helper_mode_fixup(struct drm_crtc *crtc, const struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode){ return true;}EXPORT_IF_KUNIT(amdgpu_dm_crtc_helper_mode_fixup);
STATIC_IFN_KUNIT int amdgpu_dm_crtc_helper_atomic_check(struct drm_crtc *crtc, struct drm_atomic_commit *state){ struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); struct amdgpu_device *adev = drm_to_adev(crtc->dev); struct dc *dc = adev->dm.dc; struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); int ret = -EINVAL;
trace_amdgpu_dm_crtc_atomic_check(crtc_state);
amdgpu_dm_crtc_update_crtc_active_planes(crtc, crtc_state);
if (WARN_ON(unlikely(!dm_crtc_state->stream && amdgpu_dm_crtc_modeset_required(crtc_state, NULL, dm_crtc_state->stream)))) { return ret; }
/* * We require the primary plane to be enabled whenever the CRTC is, otherwise * drm_mode_cursor_universal may end up trying to enable the cursor plane while all other * planes are disabled, which is not supported by the hardware. And there is legacy * userspace which stops using the HW cursor altogether in response to the resulting EINVAL. */ if (crtc_state->enable && !(crtc_state->plane_mask & drm_plane_mask(crtc->primary))) { DRM_DEBUG_ATOMIC("Can't enable a CRTC without enabling the primary plane\n"); return -EINVAL; }
/* * Only allow async flips for fast updates that don't change the FB * pitch, the DCC state, rotation, etc. */ if (crtc_state->async_flip && dm_crtc_state->update_type != UPDATE_TYPE_FAST) { drm_dbg_atomic(crtc->dev, "[CRTC:%d:%s] async flips are only supported for fast updates\n", crtc->base.id, crtc->name); return -EINVAL; }
if (!state->legacy_cursor_update && amdgpu_dm_crtc_vrr_active(dm_crtc_state)) { struct drm_plane_state *primary_state;
/* Pull in primary plane for correct VRR handling */ primary_state = drm_atomic_get_plane_state(state, crtc->primary); if (IS_ERR(primary_state)) return PTR_ERR(primary_state); }
/* In some use cases, like reset, no stream is attached */ if (!dm_crtc_state->stream) return 0;
if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK) return 0;
DRM_DEBUG_ATOMIC("Failed DC stream validation\n"); return ret;}EXPORT_IF_KUNIT(amdgpu_dm_crtc_helper_atomic_check);
static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = { .disable = amdgpu_dm_crtc_helper_disable, .atomic_check = amdgpu_dm_crtc_helper_atomic_check, .mode_fixup = amdgpu_dm_crtc_helper_mode_fixup, .get_scanout_position = amdgpu_crtc_get_scanout_position,};
/* * This hysteresis filter as configured will: * * * Search through the latest 8[filter_history_size] entries in history, * skipping entries that are older than [filter_old_history_threshold] frames * (0 means ignore age) * * Searches for short-idle-periods that lasted shorter than * 4[filter_num_frames] frames-times * * If there is at least 1[filter_entry_count] short-idle-period, then a delay * of 4[activation_num_delay_frames] will applied before allowing idle * optimizations again. * * An additional delay of 11[sso_num_frames] is applied before enabling * panel-specific optimizations. * * The values were determined empirically on another OS, optimizing for Z8 * residency on APUs when running a productivity + web browsing test. * * TODO: Run similar tests to determine if these values are also optimal for * Linux, and if each APU generation benefits differently. */static struct amdgpu_dm_ism_config default_ism_config = { .filter_num_frames = 4, .filter_history_size = 8, .filter_entry_count = 1, .activation_num_delay_frames = 4, .filter_old_history_threshold = 0, .sso_num_frames = 11,};
int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, struct drm_plane *plane, uint32_t crtc_index){ struct amdgpu_crtc *acrtc = NULL; struct drm_plane *cursor_plane; bool has_degamma; int res = -ENOMEM;
cursor_plane = kzalloc_obj(*cursor_plane); if (!cursor_plane) goto fail;
cursor_plane->type = DRM_PLANE_TYPE_CURSOR; res = amdgpu_dm_plane_init(dm, cursor_plane, 0, NULL);
acrtc = kzalloc_obj(struct amdgpu_crtc); if (!acrtc) goto fail;
res = drm_crtc_init_with_planes( dm->ddev, &acrtc->base, plane, cursor_plane, &amdgpu_dm_crtc_funcs, NULL);
if (res) goto fail;
amdgpu_dm_ism_init(&acrtc->ism, &default_ism_config);
drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
/* Create the plane state */ if (acrtc->base.funcs->atomic_create_state) { struct drm_crtc_state *crtc_state;
crtc_state = acrtc->base.funcs->atomic_create_state(&acrtc->base); if (IS_ERR(crtc_state)) { res = PTR_ERR(crtc_state); goto error_ism_fini; }
acrtc->base.state = crtc_state; }
acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size; acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
acrtc->crtc_id = crtc_index; acrtc->base.enabled = false; acrtc->otg_inst = -1;
dm->adev->mode_info.crtcs[crtc_index] = acrtc;
/* Don't enable DRM CRTC degamma property for * 1. DCE since it doesn't support programmable degamma anywhere. * 2. DCN401 since pre-blending degamma LUT doesn't apply to cursor. * Note: DEGAMMA properties are created even if the primary plane has the * COLOR_PIPELINE property. User space can use either the DEGAMMA properties * or the COLOR_PIPELINE property. An atomic commit which attempts to enable * both is rejected. */ has_degamma = dm->adev->dm.dc->caps.color.dpp.dcn_arch && dm->adev->dm.dc->ctx->dce_version != DCN_VERSION_4_01;
drm_crtc_enable_color_mgmt(&acrtc->base, has_degamma ? MAX_COLOR_LUT_ENTRIES : 0, true, MAX_COLOR_LUT_ENTRIES);
drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);
#ifdef AMD_PRIVATE_COLOR dm_crtc_additional_color_mgmt(&acrtc->base);#endif return 0;
error_ism_fini: amdgpu_dm_ism_flush(&acrtc->ism); drm_crtc_cleanup(&acrtc->base);fail: kfree(acrtc); kfree(cursor_plane); return res;}EXPORT_IF_KUNIT(amdgpu_dm_crtc_init);