Something went wrong. Try again.
(I'm so sorry!) Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
Something went wrong. Try again.
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363/* * Copyright 2021 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */
#include "amdgpu_reset.h"#include "aldebaran.h"#include "sienna_cichlid.h"#include "smu_v13_0_10.h"#include "soc_v1_0.h"
static int amdgpu_reset_xgmi_reset_on_init_suspend(struct amdgpu_device *adev){ int i;
for (i = adev->num_ip_blocks - 1; i >= 0; i--) { if (!adev->ip_blocks[i].status.valid) continue; if (!adev->ip_blocks[i].status.hw) continue; /* displays are handled in phase1 */ if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) continue;
/* XXX handle errors */ amdgpu_ip_block_suspend(&adev->ip_blocks[i]); adev->ip_blocks[i].status.hw = false; }
/* VCN FW shared region is in frambuffer, there are some flags * initialized in that region during sw_init. Make sure the region is * backed up. */ amdgpu_vcn_save_vcpu_bo(adev);
return 0;}
static int amdgpu_reset_xgmi_reset_on_init_prep_hwctxt( struct amdgpu_reset_control *reset_ctl, struct amdgpu_reset_context *reset_context){ struct list_head *reset_device_list = reset_context->reset_device_list; struct amdgpu_device *tmp_adev; int r;
list_for_each_entry(tmp_adev, reset_device_list, reset_list) { amdgpu_unregister_gpu_instance(tmp_adev); r = amdgpu_reset_xgmi_reset_on_init_suspend(tmp_adev); if (r) { dev_err(tmp_adev->dev, "xgmi reset on init: prepare for reset failed"); return r; } }
return r;}
static int amdgpu_reset_xgmi_reset_on_init_restore_hwctxt( struct amdgpu_reset_control *reset_ctl, struct amdgpu_reset_context *reset_context){ struct list_head *reset_device_list = reset_context->reset_device_list; struct amdgpu_device *tmp_adev = NULL; int r;
r = amdgpu_device_reinit_after_reset(reset_context); if (r) return r; list_for_each_entry(tmp_adev, reset_device_list, reset_list) { if (!tmp_adev->kfd.init_complete) { kgd2kfd_init_zone_device(tmp_adev); amdgpu_amdkfd_device_init(tmp_adev); amdgpu_amdkfd_drm_client_create(tmp_adev); amdgpu_ptl_sysfs_init(tmp_adev); } }
return r;}
static int amdgpu_reset_xgmi_reset_on_init_perform_reset( struct amdgpu_reset_control *reset_ctl, struct amdgpu_reset_context *reset_context){ struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle; struct list_head *reset_device_list = reset_context->reset_device_list; struct amdgpu_device *tmp_adev = NULL; int r;
dev_dbg(adev->dev, "xgmi roi - hw reset\n");
list_for_each_entry(tmp_adev, reset_device_list, reset_list) { mutex_lock(&tmp_adev->reset_cntl->reset_lock); tmp_adev->reset_cntl->active_reset = amdgpu_asic_reset_method(adev); } r = 0; /* Mode1 reset needs to be triggered on all devices together */ list_for_each_entry(tmp_adev, reset_device_list, reset_list) { /* For XGMI run all resets in parallel to speed up the process */ if (!queue_work(system_dfl_wq, &tmp_adev->xgmi_reset_work)) r = -EALREADY; if (r) { dev_err(tmp_adev->dev, "xgmi reset on init: reset failed with error, %d", r); break; } }
/* For XGMI wait for all resets to complete before proceed */ if (!r) { list_for_each_entry(tmp_adev, reset_device_list, reset_list) { flush_work(&tmp_adev->xgmi_reset_work); r = tmp_adev->asic_reset_res; if (r) break; } }
list_for_each_entry(tmp_adev, reset_device_list, reset_list) { mutex_unlock(&tmp_adev->reset_cntl->reset_lock); tmp_adev->reset_cntl->active_reset = AMD_RESET_METHOD_NONE; }
return r;}
int amdgpu_reset_do_xgmi_reset_on_init( struct amdgpu_reset_context *reset_context){ struct list_head *reset_device_list = reset_context->reset_device_list; struct amdgpu_device *adev; int r;
if (!reset_device_list || list_empty(reset_device_list) || list_is_singular(reset_device_list)) return -EINVAL;
adev = list_first_entry(reset_device_list, struct amdgpu_device, reset_list); r = amdgpu_reset_prepare_hwcontext(adev, reset_context); if (r) return r;
r = amdgpu_reset_perform_reset(adev, reset_context);
return r;}
struct amdgpu_reset_handler xgmi_reset_on_init_handler = { .reset_method = AMD_RESET_METHOD_ON_INIT, .prepare_env = NULL, .prepare_hwcontext = amdgpu_reset_xgmi_reset_on_init_prep_hwctxt, .perform_reset = amdgpu_reset_xgmi_reset_on_init_perform_reset, .restore_hwcontext = amdgpu_reset_xgmi_reset_on_init_restore_hwctxt, .restore_env = NULL, .do_reset = NULL,};
int amdgpu_reset_init(struct amdgpu_device *adev){ int ret = 0;
switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { case IP_VERSION(13, 0, 2): case IP_VERSION(13, 0, 6): case IP_VERSION(13, 0, 12): case IP_VERSION(13, 0, 14): ret = aldebaran_reset_init(adev); break; case IP_VERSION(11, 0, 7): ret = sienna_cichlid_reset_init(adev); break; case IP_VERSION(13, 0, 10): ret = smu_v13_0_10_reset_init(adev); break; case IP_VERSION(15, 0, 8): ret = soc_v1_0_reset_init(adev); break; default: break; }
return ret;}
int amdgpu_reset_fini(struct amdgpu_device *adev){ int ret = 0;
switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { case IP_VERSION(13, 0, 2): case IP_VERSION(13, 0, 6): case IP_VERSION(13, 0, 12): case IP_VERSION(13, 0, 14): ret = aldebaran_reset_fini(adev); break; case IP_VERSION(11, 0, 7): ret = sienna_cichlid_reset_fini(adev); break; case IP_VERSION(13, 0, 10): ret = smu_v13_0_10_reset_fini(adev); break; case IP_VERSION(15, 0, 8): ret = soc_v1_0_reset_fini(adev); break; default: break; }
return ret;}
int amdgpu_reset_prepare_hwcontext(struct amdgpu_device *adev, struct amdgpu_reset_context *reset_context){ struct amdgpu_reset_handler *reset_handler = NULL;
if (adev->reset_cntl && adev->reset_cntl->get_reset_handler) reset_handler = adev->reset_cntl->get_reset_handler( adev->reset_cntl, reset_context); if (!reset_handler) return -EOPNOTSUPP;
return reset_handler->prepare_hwcontext(adev->reset_cntl, reset_context);}
int amdgpu_reset_perform_reset(struct amdgpu_device *adev, struct amdgpu_reset_context *reset_context){ int ret; struct amdgpu_reset_handler *reset_handler = NULL;
if (adev->reset_cntl) reset_handler = adev->reset_cntl->get_reset_handler( adev->reset_cntl, reset_context); if (!reset_handler) return -EOPNOTSUPP;
ret = reset_handler->perform_reset(adev->reset_cntl, reset_context); if (ret) return ret;
return reset_handler->restore_hwcontext(adev->reset_cntl, reset_context);}
void amdgpu_reset_destroy_reset_domain(struct kref *ref){ struct amdgpu_reset_domain *reset_domain = container_of(ref, struct amdgpu_reset_domain, refcount); if (reset_domain->wq) destroy_workqueue(reset_domain->wq);
kvfree(reset_domain);}
struct amdgpu_reset_domain *amdgpu_reset_create_reset_domain(enum amdgpu_reset_domain_type type, char *wq_name){ struct amdgpu_reset_domain *reset_domain;
reset_domain = kvzalloc_obj(struct amdgpu_reset_domain); if (!reset_domain) { DRM_ERROR("Failed to allocate amdgpu_reset_domain!"); return NULL; }
reset_domain->type = type; kref_init(&reset_domain->refcount);
reset_domain->wq = create_singlethread_workqueue(wq_name); if (!reset_domain->wq) { DRM_ERROR("Failed to allocate wq for amdgpu_reset_domain!"); amdgpu_reset_put_reset_domain(reset_domain); return NULL;
}
atomic_set(&reset_domain->in_gpu_reset, 0); atomic_set(&reset_domain->reset_res, 0); init_rwsem(&reset_domain->sem);
return reset_domain;}
void amdgpu_device_lock_reset_domain(struct amdgpu_reset_domain *reset_domain){ atomic_set(&reset_domain->in_gpu_reset, 1); down_write(&reset_domain->sem);}
void amdgpu_device_unlock_reset_domain(struct amdgpu_reset_domain *reset_domain){ atomic_set(&reset_domain->in_gpu_reset, 0); up_write(&reset_domain->sem);}
void amdgpu_reset_get_desc(struct amdgpu_reset_context *rst_ctxt, char *buf, size_t len){ if (!buf || !len) return;
switch (rst_ctxt->src) { case AMDGPU_RESET_SRC_JOB: if (rst_ctxt->job) { snprintf(buf, len, "job hang on ring:%s", rst_ctxt->job->base.sched->name); } else { strscpy(buf, "job hang", len); } break; case AMDGPU_RESET_SRC_RAS: strscpy(buf, "RAS error", len); break; case AMDGPU_RESET_SRC_MES: strscpy(buf, "MES hang", len); break; case AMDGPU_RESET_SRC_HWS: strscpy(buf, "HWS hang", len); break; case AMDGPU_RESET_SRC_USER: strscpy(buf, "user trigger", len); break; case AMDGPU_RESET_SRC_USERQ: strscpy(buf, "user queue trigger", len); break; default: strscpy(buf, "unknown", len); }}
bool amdgpu_reset_in_recovery(struct amdgpu_device *adev){ return (adev->init_lvl->level == AMDGPU_INIT_LEVEL_RESET_RECOVERY);}