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OR-1 dataflow CPU sketch
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1.0 kB · 37 lines
Python
at main
1234567891011121314151617181920212223242526272829303132333435363738from dataclasses import dataclassfrom typing import Optional
from cm_inst import FrameSlotValue, Instructionfrom emu.events import EventCallbackfrom sm_mod import Presencefrom tokens import CMToken
@dataclass(frozen=True)class DeferredRead: cell_addr: int return_route: CMToken
@dataclass(frozen=True)class PEConfig: pe_id: int = 0 iram: dict[int, Instruction] | None = None frame_count: int = 8 frame_slots: int = 64 matchable_offsets: int = 8 lane_count: int = 4 initial_frames: Optional[dict[int, list[FrameSlotValue]]] = None initial_tag_store: Optional[dict[int, tuple[int, int]]] = None allowed_pe_routes: Optional[set[int]] = None allowed_sm_routes: Optional[set[int]] = None on_event: EventCallback | None = None
@dataclass(frozen=True)class SMConfig: sm_id: int cell_count: int = 512 initial_cells: Optional[dict[int, tuple[Presence, Optional[int]]]] = None tier_boundary: int = 256 on_event: EventCallback | None = None