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OR-1 dataflow CPU sketch
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1.8 kB · 93 lines
at main
12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394; ==========================================; dfasm syntax highlighting test program; ==========================================
; --- System pragma ---@system pe=3, sm=1, iram=128, ctx=2
; --- Data definitions ---@val|sm0:5 = 0x42@msg|sm0:0 = 'h', 'e', 'l', 'l', 'o'@greeting = #str "hello\nworld"@path = r"no\escapes\here"@raw = b"\x01\x02\x03"
; --- Location directive ---@data_section|sm0:
; --- Instruction definitions ---&c1|pe0 <| const, 3&c2|pe0 <| const, 0xFF&result|pe0 <| add&output|pe1 <| pass&branch|pe2 <| sweq&serial|pe0 <| ior, dest=0x45, addr=0x91, data=0x43&reader|pe1 <| read, 5
; --- Plain edges ---&c1|pe0 |> &result|pe0:L&c2|pe0 |> &result|pe0:R&result|pe0 |> &output|pe1:L&result|pe0 |> &branch|pe2:L
; --- Strong inline edge ---add &c1, &c2 |> &output, &branch
; --- Weak inline edge ---&output, &branch sub <| &c1, &c2
; --- Function definition ---$fib |> { &const_n <| const, 10 &sub1 <| sub &branch <| sweq &const_n |> &branch:L &sub1 |> &branch:R}
; --- All opcodes ---&op_add <| add&op_sub <| sub&op_inc <| inc&op_dec <| dec&op_shiftl <| shiftl&op_shiftr <| shiftr&op_ashiftr <| ashiftr&op_and <| and&op_or <| or&op_xor <| xor&op_not <| not&op_eq <| eq&op_lt <| lt&op_lte <| lte&op_gt <| gt&op_gte <| gte&op_breq <| breq&op_brgt <| brgt&op_brge <| brge&op_brof <| brof&op_brty <| brty&op_sweq <| sweq&op_swgt <| swgt&op_swge <| swge&op_swof <| swof&op_swty <| swty&op_gate <| gate&op_sel <| sel&op_merge <| merge&op_pass <| pass&op_const <| const, 0&op_free_ctx <| free_ctx&op_read <| read&op_write <| write&op_clear <| clear&op_alloc <| alloc&op_free <| free&op_rd_inc <| rd_inc&op_rd_dec <| rd_dec&op_cmp_sw <| cmp_sw&op_ior <| ior&op_iow <| iow&op_iorw <| iorw&op_load <| load_inst&op_route <| route_set